In more recent chip designs, memories occupy a large percentage of the chip area. With advances in technology, more and more memory cells are closely packed, thereby increasing the number of faults being detected on the memory. In order to test the memories for all possible fault types, a comprehensive memory built-in self-test (BIST) solution is required. Memories are generally grouped together based on the memory type and a group of memories are tested by a single BIST engine in parallel. In order to test the memories thoroughly and minimize the impact to test time, there are multiple BIST engines in a chip, operating in parallel and thereby testing multiple groups of memories in parallel. In current technology, up to 16 memories are able to share, as a group, a single BIST engine.
Today, both at manufacturing test, and during system test modes, when testing memories using BIST, the BIST engines are activated at the same time. Each BIST engine will start testing a plurality of memories (e.g., 16) associated with it in parallel. As all the memories start read/write operation in parallel, and in a concurrent fashion, a considerable amount of current is abruptly demanded from the power supply network. This sudden and abrupt demand on the power supply at the start of the BIST execution can result in a memory functional failure or a functional failure in the BIST logic itself.
Prior attempts to mitigate BIST startup power demand issues within the memory design include sending “dummy read” instructions to memory for many cycles, in order to allow the power supply time to settle, prior to providing any real operations to the memories. This effectively deals with the problem of memories failing due to temporary power supply voltage integrity, by letting the memories fail for a short duration, until the power supply network voltage settles to a more reasonable voltage, at which time the memories are expected to function. But, this method does nothing to address the BIST logic functionality issues that may arise due to sudden and abrupt demands on the power supply. While the memories are allowed to fail during this short time period, the BIST logic is still expected to function correctly.
However, the BIST circuit may not work correctly if the power supply voltage actually exceeds the voltage range used during the design analysis specific to BIST logic timing closure. At-speed BIST may place a significant and abrupt demand on the power supply especially when the BIST starts execution. The sudden demand in power supply current at the start of memory BIST, due to all BIST engines starting operation, in parallel, will contribute to a large voltage bounce in the power supply to the memories and the BIST logic, due to the L*(di/dt) component of the power supply network. This large bounce can lead to memory failures and incorrect values getting captured in one or more state elements of the BIST logic. The BIST logic will be especially sensitive when running with an edge-based clock mode, when hold time margin is of the most concern.
This disclosure addresses this power demand issue at the start of the BIST execution, by executing the start of BIST patterns in such a way as to limit the abruptness of the sudden demand on the power supply.